View BM81004MUV-ZE2_8603599.PDF datasheet online --- IC-ON-LINE

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datashee t product structure silicon monolithic chip this chip is not designed for protection against ratio active ray s. 1/ 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 14 ? 001 power supply ic series for tft-lcd panels 12v input multi-channel system power supply ic bm81004muv general description bm81004muv is a system power supply for tft-lcd panels used for liquid crystal tvs. this ic is incorporated with negative and positive charge pump controller and gate pulse modulation (gpm) function. it also features built- in eeprom to contain each setting voltage, soft start time etc. features step-up dc/dc converter (avdd). (synchronous rectification, built-in load switch). step- dow n dc/dc converter 1(vio). (non-synchronous rectification). step-down dc/dc converter 2(vcore). step-down dc/dc converter 3(havdd). (synchronous rectification). positive charge pump controller (vgh). negative charge pump controller (vgl). gate pulse modulation (gpm) function. high voltage ldo (50ma) 10 bit dac-controlled gamma amplifier 4ch 8 bit dac-controlled vcom amplifier output voltage control by i2c. built-in eeprom. switching frequency 750khz (avdd, vio). switching frequency 1mhz (vcore, havdd). applications tft-lcd panel typical application circuit 1 top view key specifications ? input voltage range 8.6v to 14.0v ? avdd output voltage range 11.7v to 18.0v ? vio output voltage range 2.2v to 3.7v ? havdd output voltage range 4.8v to 11.1v ? vgh output voltage range 25v to 40.5v ? vgl output voltage range -10.2v to -4.0v ? switching frequency 750khz(typ) 1mhz(typ) ? operating temperature range - 40 to + 10 5 package w(typ) x d(typ) x h(max) vqfn48v7070a 7.00mm x 7.00mm x 1.0 mm vio amp2 bm81004muv amp1vdd1 pg sda scl a0 avin hvldo hvcc vdd2 vinb2 vinb1 vinb1 n.c. swb1 swb1 ampgnd amp4 amp3 en vdd3 pgnd3 swb3 n.c. vinb3 re vghm vgh drvp swo swi swsw pgndpgnd vl comp agnd ctrl vcore havdd vin vin vin avdd vgl swb1 avdd sw vgh sw vcominn pgnd2 swb2 drvn vgl pgate avdds avdd figure 1 . application circuit 1 downloaded from: http:///
2/ 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv typical application circuit 2 top view vio amp2 bm81004muv amp1 vdd1 pg sda scl a0 avin hvldo hvcc vdd2 vinb2 vinb1 vinb1 n.c. swb1 swb1 ampgnd amp4 amp3 en vdd3 pgnd3 swb3 n.c. vinb3 re vghm vgh drvp swo swi swsw pgnd pgnd vl comp agnd ctrl vcore havdd vin vin vin avdd vgl swb1 avdd sw vgh sw vcom inn pgnd2 swb2 drvn vgl pgate avdds avdd figure 2 . application circuit 2 downloaded from: http:///
3/ 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv contents general description ........................................................................................................................................................................ 1 features .......................................................................................................................................................................................... 1 applications .................................................................................................................................................................................... 1 typical application circuit 1 ............................................................................................................................................................ 1 key specifications ........................................................................................................................................................................... 1 package .......................................................................................................................................................................................... 1 typical application circuit 2 ............................................................................................................................................................ 2 pin configuration ............................................................................................................................................................................ 4 pin description ................................................................................................................................................................................ 4 block diagram ................................................................................................................................................................................ 5 description of each block ............................................................................................................................................................... 6 absolute maximum ratings ............................................................................................................................................................ 7 recommended operating ranges ................................................................................................................................................. 7 electrical characteristics ................................................................................................................................................................ . 8 typical performance curves ......................................................................................................................................................... 12 timing chart ................................................................................................................................................................................. 24 example application ..................................................................................................................................................................... 25 protection function explanation of each block ............................................................................................................................... 26 protection function list ................................................................................................................................................................... 29 serial transmission ....................................................................................................................................................................... 30 register map ................................................................................................................................................................................ 33 command table 1 ......................................................................................................................................................................... 34 command table 2 ......................................................................................................................................................................... 35 selecting application componen ts ............................................................................................................................................... 36 layout guideline ............................................................................................................................................................................. 41 power dissipation ......................................................................................................................................................................... 41 i/o equivalence circuit ................................................................................................................................................................ . 42 operational notes ......................................................................................................................................................................... 45 ordering information ..................................................................................................................................................................... 47 marking diagram .......................................................................................................................................................................... 47 physical dimension tape and reel information ............................................................................................................................ 48 revision history ............................................................................................................................................................................ 49 downloaded from: http:///
4/ 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv pin conf ig uration (top view) 22 21 20 19 18 17 16 15 14 13 39 40 41 42 43 44 45 46 47 48 10 9 8 7 6 5 4 3 2 1 27 28 29 30 31 32 33 34 35 36 amp2 amp1 vdd1 pg sda scl a0 avin hvldo hvcc en vdd3 pgnd3 swb3 n.c. vinb3 re vghm vgh drvp ctrl agnd comp vl pgnd pgnd sw sw swi swo amp3 amp 4 swb 1 swb 1 n . c . vinb 1 vinb 1 vinb 2 vdd 2 thermal pad ampgnd 25 26 drvn vgl 24 23 avdds pgate 37 38 swb 2 pgnd2 12 11 vcom inn figure 3 . pin configuration pin description pin no. symbol function pin no. symbol function 1 amp2 gamma amplifier output pin 2 25 vgl negative charge pump output pin 2 amp1 gamma amplifier output pin 1 26 drvn negative charge pump drive pin 3 vdd1 step-down dc/dc output pin 1 27 drvp positive charge pump drive pin 4 pg power good signal output pin 28 vgh positive charge pump output pin 5 sda serial data input pin 29 vghm gpm output pin 6 scl serial clock input pin 30 re gpm slope adjustment pin 7 a0 i2c address selected pin 31 vinb3 power supply pin for step-down dc/dc 3 8 avin power supply input pin 32 n.c. D 9 hvldo high voltage ldo output pin 33 swb3 step-down dc/dc switching pin 3 10 hvcc vcom and gamma power supply pin 34 pgnd3 step-down dc/dc gnd pin 3 11 vcom vcom amplifier output pin 35 vdd3 step-down dc/dc output pin 3 12 inn vcom amplifier feedback pin 36 en enable pin 13 ctrl gpm control pin 37 pgnd2 step-down dc/dc gnd pin 2 14 agnd analog gnd pin 38 swb2 step-down dc/dc switching pin 2 15 comp error amplifier output pin 39 vdd2 step-down dc/dc output pin 2 16 vl internal reg output pin 40 vinb2 power supply pin for step-down dc/dc 2 17 pgnd step-up dc/dc gnd pin 41 vinb1 power supply pin for step-down dc/dc 1 18 pgnd step-up dc/dc gnd pin 42 vinb1 power supply pin for step-down dc/dc 1 19 sw step-up dc/dc switching pin 43 n.c. D 20 sw step-up dc/dc switching pin 44 swb1 step-down dc/dc switching pin 1 21 swi load switch input pin 45 swb1 step-down dc/dc switching pin 1 22 swo load switch output pin 46 ampgnd gamma amplifier gnd pin 23 avdds step-up dc/dc feedback pin 47 amp4 gamma amplifier output pin 4 24 pgate load switch gate drive pin 48 amp3 gamma amplifier output pin 3 downloaded from: http:///
5/ 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv block diagram boost converter buck converter 3 vgh regulator gpm dac i2c interface eeprom internal regulator avin buck converter 1 buck converter 2 sequence control sw vgl swb1 comp swo swi sw pgnd vinb1 swb1 vdd1 vinb2 swb2 pgnd2 vdd2 vinb3 swb3 pgnd3 vdd3 drvp vgh vghm re ctrl drvn vgl agnd pg en a0 scl sda vl vin havdd vcore vio vin vin vgl sw avdd vgh pgate avdds avdd vin hvldo hvcc hvldo hvldo avdd opamp + - vcom amp1 + - amp2 + - amp4 + - amp3 + - hvldo dac ampgnd hvcc hvcc inn hvcc figure 4 . block diagram downloaded from: http:///
6/ 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv description of each block buck converter block 2 this block generates vcore (vdd2) voltage from power supply voltage. after releasing uvlo of vin, vl starts activating. after auto read is operated t o eeprom, vcore will be activated. during operations, it is possible to prevent destruction of ic by ov p, uvp and ocp protection function. buck converter block 1 this block generates vio (vdd1) voltage from power supply voltage of vio . after completing vcore start-up, vio starts activating. power on reset works at the time of vin startup and the setting that is writte n to eeprom will be reflected in register. during operations, it is possible to prevent destruction of ic by ov p, uvp and ocp protection function. vgl regulator block this block generates vgl voltage. after completing vcore start-up, vgl starts activating. power on reset works at the time of vin startup and the setting that is writte n to eeprom will be reflected in register. during operations, it is possible to prevent destruction of ic by uvp and ocp protection function. boost converter block this block generates avdd (swo) voltage from power supply voltage. it activates when en=h, and under condition where vio and vgl are activatin g. power on reset works at the time of vin startup and the setting that is writte n to eeprom will be reflected in register. during operations, it is possible to prevent destruction of ic by ovp, uvp and ocp protection function. buck converter block 3 this block generates havdd (vdd3) voltage from power supply voltage. havdd starts up following avdd output voltage. the setting voltage range of the havdd voltage depends on the avdd s etting voltage, and the lower limit level of th e havdd voltage is limited in avdd 0.4. power on reset works at the time of vin startup and the setting that is writte n to eeprom will be reflected in register. during operations, it is possible to prevent destruction of ic by ov p, uvp and ocp protection function. high voltage ldo block this block generates hvldo voltage from power supply voltage of avdd (hvcc). hvldo starts up following avdd output voltage. power on reset works at the time of vin startup and the setting that is writte n to eeprom will be reflected in register. during operations, it is possible to prevent destruction of ic by uvp and ocp protection function. vcom amplifier block this block generates vcom voltage from power supply voltage of avdd (hvc c). vcom calibrator function is built- in. vcom starts up following avdd output voltage. power on reset works at the time of vin startup and the setting that is writte n to eeprom will be reflected in register. gamma amplifier block this block generates amp1 to 4 voltages from power supply volt age of avdd (hvcc). amp1 to 4 startup following avdd output voltage. power on reset works at the time of vin startup and the setting that is writte n to eeprom will be reflected in register. vgh regulator block this block generates vgh voltage from avdd volta ge. after completing avdd start-up, vgh starts activating. power on reset works at the time of vin startup and the setting that is writte n to eeprom will be reflected in register. during operations, it is possible to prevent destruction of ic by ovp, uvp and ocp protection function. gpm block this is a switching circuit to drive a gate voltage for tft that con sist of pmos fet. vghm output synchronizes with ctrl input and outputs high voltage = vgh at ctrl=h. gpm falling limit voltage can be controlled by eeprom. caution ? en input tolerant function is built in this ic. no need to be alway s en < vin. ? when pg pin is not used, pg pin must be connect ed to gnd, or it should be open. downloaded from: http:///
7/ 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv absolute maximum ratings *1 it shows junction temperature when stores. *2 derate by 40.6mw/ at ta > 25 (o n 4-layer 76.2mm 114.3mm 1.6mm glass epoxy board). recommended operating ranges (ta=- 40 105 ) parameter symbol limits unit min typ max supply voltage avin 8.6 - 14 v functional pin voltage en, a0, ctrl -0.1 - 5.5 v 2 wire serial pin voltage sd a, scl -0.1 - 5.5 v 2 wire serial frequency fclk - - 400 khz parameter symbol limits unit min typ max supply voltage avin, vinb1, vinb2, vinb3 -0.3 - 24 v hvcc -0.3 - 20 v input voltage sda, scl, a0, en, ctrl -0.3 - 7 v output voltage vl -0.3 - 6.5 v comp, pg -0.3 - 7 v sw, swi, swo, pgate, avdds, vdd1, swb1, vdd2, swb2, vdd3, swb3 -0.3 - 24 v hvldo, vcom, inn amp1, amp2, amp3, amp4 -0.3 - 20 v vgl, drvn - 15 - 7 v drvp, vgh, vghm, re -0.3 - 48 v operating ambient temperature range ta - 40 - 105 storage temperature range tstg - 55 - 150 maximum continuous junction temperature tjmax (*1) - - 150 power dissipation (*2) pd 5.08 w ja 24.6 degc/w downloaded from: http:///
8/ 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv electrical characteristics (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v) parameter symbol limits unit condition min typ max general vin under voltage lockout threshold vin_ uvlo 8.0 8.3 8.6 v vin rising 7.25 7.55 7.85 v vin falling thermal shutdown tsd 155 175 19 5 de sign guarantee internal oscillator frequency 1 fosc1 600 750 900 khz avdd, vio, 0 < ta < 50 internal oscillator frequency 2 fosc2 800 1000 1200 khz vcore, havdd, 0 < ta < 50 vl voltage vl 4.9 5 5.1 v consumption current icc - 5.4 - ma not switching logic signals sda, scl, en, a0, ctrl high level input voltage vih 2 - - v low level input voltage vil - - 0.5 v minimum output voltage vsda - - 0.4 v sda, isda=3ma pull-down resistance rlogic 140 200 260 k en, a0, ctrl boost converter (avdd) output voltage range avdd 11.7 - 18.0 v 0.1v step regulation voltage avdd_r 15.444 15.6 15.756 v 27h, 1%, 0 < ta < 50 hi -side leakage current ilk_swh - 0 10 ua swi=18v, sw=0v hi -side sw on-resistance ron_swh - 100 200 m isw=-500ma lo -side sw leakage current ilk_swl - 0 10 ua sw=18v lo -side sw on-resistance ron_swl - 100 200 m isw=500ma load sw on-resistance ron_ls - 100 200 m ils=500ma sw current limit ilim_sw 4.25 5 5.75 a 5.0a C offset(0.0a) setting l=6.8uh, 0 < ta < 50 sw current limit offset ilim_set 0 - 2.8 a 0.4a step over-voltage protection rise vovp_avd d_rise 18 19.5 21 v over-voltage protection fall vovp_avd d_fall - 18 - v avdd uvp detecting voltage vuvp_ avdd - avdd x 0.8 - v soft start time tss_ avdd 10 - 20 msec load switch current limit ilim_lsw - 7 - a external load switch current limit ilim_ext 450 540 630 mv pgate drive capability pgate_ drv - 10 - ua downloaded from: http:///
9/ 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv electrical characteristics (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v) parameter symbol limits unit condition min typ max buck converter 1 (vio) output voltage range vio 2.2 - 3.7 v 0.1v step regulation voltage vio_r 3.234 3.3 3.366 v 0bh, 2%, 0 < ta < 50 hi -side swb1 leak current ilk_ swb1h - 0 10 ua vinb1=18v, swb1=0v hi -side swb1 on-resistance ron_ swb1h - 200 300 m swb1=-500ma swb1 current limit ilim_ swb1 2.8 3.5 4.2 a l=6.8uh, 0 < ta < 50 vio over-voltage protection vovp_ vio vio x 1.03 vio x 1.1 vio x 1.17 v vio uvp detecting voltage vuvp_ vio - vio x 0.8 - v frequency 1/4 soft start time tss_vio - 3.3 - msec vio=3.3v buck converter 2 (vcore) vcore reference voltage vcore_ ref 0.396 0.400 0.404 v 1%, ta=25 0.394 0.400 0.406 v 1.5%, 0 < ta < 50 hi -side swb2 leak current ilk_ swb2h - 0 10 ua vinb2=18v, swb2=0v hi -side swb2 on-resistance ron_ swb2h - 175 300 m swb2=-500ma lo -side swb2 leak current ilk_ swb2l - 0 10 ua swb2=18v lo -side swb2 on-resistance ron_ swb2l - 175 30 0 m swb2=500ma swb2 current limit ilim_ swb2 2.4 3.0 3.6 a l=6.8uh, 0 < ta < 50 vcore over-voltage protection vovp_ vcore vcore x 1.03 vcore x 1.1 vcore x 1.17 v vcore uvp detecting voltage vuvp_ vcore - vcore x 0.8 - v frequency 1/4 soft start time tss_ vcore - 3 - msec buck converter 3 (havdd) output voltage range havdd 4.8 - 11.1 v 0.1v step regulation voltage havdd_r 7.68 7.8 7.92 v 1eh, 1.5%, 0 < ta < 50 hi -side swb3 leak current ilk_ swb3h - 0 10 ua vinb3=18v, swb3=0v hi -side swb3 on-resistance ron_ swb3h - 300 500 m swb3=-500ma lo -side swb3 leak current ilk_ swb3l - 0 10 ua swb3=18v lo -side swb3 on-resistance ron_ swb3l - 300 500 m swb3=500ma swb3 current limit ilim_ swb3 1.2 1.8 2.4 a l=6.8uh, 0 < ta < 50 havdd over-voltage protection vovp_ havdd havdd x 1.03 havdd x 1.1 havdd x 1.17 v havdd uvp detecting voltage vuvp_ havdd - havdd x 0.8 - v frequency 1/4 downloaded from: http:///
10 / 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv electrical characteristics (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v) parameter symbol limits u nit condition min typ max vgh regulator output voltage range vgh 25 - 40.5 v 0.5v step regulation voltage vgh_r 34.47 35 35.53 v 14h, 1.5%, 0 < ta < 50 io=5ma over-current protection ilim_ drvp 5 - - ma vgh over-voltage protection vovp_ vgh 42 45 48 v vgh uvp detecting voltage vuvp_ vgh - vgh x 0.8 - v soft start time tss_vgh - 7 - msec vgh=35v vgl regulator output voltage range vgl -10.2 - -4.0 v 0.2v step regulation voltage vgl_r -6.09 -6 -5.91 v 0ah, 1.5%, ta=25 io=5ma -6.12 -6 -5.88 v 0ah, 2.0%, 0 < ta < 50 io=5ma over-current protection ilim_ drvn 5 - - ma vgl uvp detecting voltage vuvp_ vgl - vgl0.8 - v delay time tdly_vgl - 2.5 - msec gate pulse modulation (gpm) vgh-vghm on-resistance rghh - 3 5 re -vghm on -resistance rghl - 3 - propagation delay tgpm 150 250 350 nsec downloaded from: http:///
11 / 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv electrical characteristics (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v) parameter symbol limits unit condition min typ max high voltage ldo output voltage range ldo 11.7 18.0 v 0.1v step regulation voltage ldo_r 15.12 15.2 15.28 v 23h, 0.5% ldo_r 15.09 15.2 15.31 v 23h, 0.7%, 0 < ta < 50 over-current protection ilim_ ldo - 100 - ma hvldo uvp detecting voltage ldo_uvp - ldox0.8 - v vcom amplifier output voltage range vcom_r hvldo x0.36 hvldo x0.54 v slew rate sr - 30 - v/usec no external components output current capability i_vcom - 200 - ma c2h load stability vo1 - 15 - mv io=-50ma 50ma dac resolution res1 8 bit dac integral non-linearity error (inl) le1 -1 - +1 lsb 02 fd is the allowable margin of error against the ideal linear. dac differential non-linearity error (dnl) dle1 -1 - +1 lsb 02 fd is the allowable margin of error against the ideal increase of 1lsb. gamma amplifier output current capability i_amp 30 - - ma load stability vo2 - 15 - mv io=-5ma 5ma dac resolution res2 10 bit dac integral non-linearity error (inl) le2 -2 - +2 lsb 00f 3f0 is the allowable margin of error against the ideal linear. dac differential non-linearity error (dnl) dle2 -2 - +2 lsb 00 f 3f 0 is the allowable margin of error against the ideal increase of 1lsb. this product has no designed for protection against radioactive rays. downloaded from: http:///
12 / 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv typical performance curves (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v, vio=3.3v, vcore=1.2v, avdd=15.6v, havdd=7.8v, vgh=35v, vgl=-6.0v, hvldo=15.2v, vcom=6.1v, gamma=7.8v, rl=no load) figure 5. input current vs input voltage (en=l, no switching) figure 6. internal oscillator frequency vs input voltage figure 7 . power-on (till avdd and vgh on) figure 8 . power-on (after avdd on) 0 1 2 3 4 5 6 7 8 5 6 7 8 9 10 11 12 13 14 15 input voltage : v in [v] input current : icc[ma] en=l no switching 500 600 700 800 900 1000 1100 1200 1300 1400 1500 5 6 7 8 9 10 11 12 13 14 15 input voltage : v in [v] internal oscillatior freqency : f osc [khz] avdd,vio frequency vcore,havdd frequency downloaded from: http:///
13 / 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv typical performance curves (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v, vio=3.3v, vcore=1.2v, avdd=15.6v, havdd=7.8v, vgh=35v, vgl=-6.0v, hvldo=15.2v, vcom=6.1v, gamma=7.8v, rl=no load) figure 9. vio efficiency vs output current figure 10 . vio output voltage vs output current figure 11 . vio load transient figure 12 . vio switching (output current=500ma) vio (100mv/div ac) i out (500ma/div) i out =500ma i out =100ma 50usec/div vio (10mv/div ac) swb1 (10v/div) i swb1 (500ma/div) i out (500ma/div) v 6.3mv 1usec/div 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 1200 1400 efficiency [%] output current [ma] vin=12v vio=3.3v -3 -2 -1 0 1 2 3 0 200 400 600 800 1000 output voltage [%] output current [ma] vin=12v vio=3.3v downloaded from: http:///
14 / 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv typical performance curves (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v, vio=3.3v, vcore=1.2v, avdd=15.6v, havdd=7.8v, vgh=35v, vgl=-6.0v, hvldo=15.2v, vcom=6.1v, gamma=7.8v, rl=no load) figure 13. vcore efficiency vs output current figure 14 . vcore output voltage vs output current figure 15 . vcore load transient figure 16 . vcore switching (output current=500ma) -3 -2 -1 0 1 2 3 0 200 400 600 800 1000 output current [ma] output voltage [%] vin=12v vcore=1.2v 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 1200 1400 output current [ma] efficiency [%] vin=12v vcore=1.2v vcore (100mv/div ac) i out (200ma/div ) i out =300ma i out =10ma 50usec/div vcore (10mv/div ac) swb2 (10v/div ) i swb2 (500ma/div ) i out (500ma/div ) v 6.4mv 1usec/div downloaded from: http:///
15 / 49 ts z02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv typical performance curves (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v, vio=3.3v, vcore=1.2v, avdd=15.6v, havdd=7.8v, vgh=35v, vgl=-6.0v, hvldo=15.2v, vcom=6.1v, gamma=7.8v, rl=no load) figure 17 . havdd efficiency vs output current (source) figure 18 . havdd output voltage vs output current (source) figure 19 . havdd load transient (source) figure 20 . havdd switching (source) (output current=500ma) -3 -2 -1 0 1 2 3 0 200 400 600 800 1000 output current [ma] output voltage [%] vin=12v avdd=15.6v havdd=7.8v source) 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 1200 1400 output current [ma] efficiency [%] vin=12v avdd=15.6v havdd=7.8v (source) havdd (100mv/div ac) i out (300ma/div) i out =350ma i out =0ma 200usec/div havdd (10mv/div ac) swb3 (10v/div) i swb3 (500ma/div) i out (500ma/div) v 6.8mv 1usec/div downloaded from: http:///
16 / 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv typical performance curves (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v, vio=3.3v, vcore=1.2v, avdd=15.6v, havdd=7.8v, vgh=35v, vgl=-6.0v, hvldo=15.2v, vcom=6.1v, gamma=7.8v, rl=no load) figure 21 . havdd efficiency vs output current (sink) figure 22 . havdd output voltage vs output current (sink) figure 23 . havdd load transient (sink) figure 24 . havdd switching (sink) (output current=500ma) -3 -2 -1 0 1 2 3 0 200 400 600 800 1000 output currnet [ma] output voltage [%] vin=12v avdd=15.6v havdd=7.8v sink) 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 1200 1400 output current [ma] efficiency [%] vin=12v avdd=15.6v havdd=7.8v (sink) havdd (100mv/div ac) i out (300ma/div) i out =350ma i out =0ma 200usec/div havdd (10mv/div ac) swb3 (10v/div) i swb3 (500ma/div) i out (500ma/div) v 9.4mv 1usec/div downloaded from: http:///
17 / 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv typical performance curves (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v, vio=3.3v, vcore=1.2v, avdd=15.6v, havdd=7.8v, vgh=35v, vgl=-6.0v, hvldo=15.2v, vcom=6.1v, gamma=7.8v, rl=no load) figure 25 . avdd efficiency vs output current figure 26 . avdd output voltage vs output current figure 27 . avdd load transient figure 28 . avdd switching (output current=500ma) avdd (10mv/div ac) sw (10v/div ) i sw (1a/div ) i out (500ma/div ) v 18.0mv 1usec/div avdd (200mv/div ac) i out (500ma/div ) i out =500ma i out =100ma 50usec/div -3 -2 -1 0 1 2 3 0 200 400 600 800 1000 output current [ma] output voltage [%] vin=12v avdd=15.6v 0 10 20 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 1200 1400 output current [ma] efficiency [%] vin=12v avdd=15.6v downloaded from: http:///
18 / 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv typical performance curves (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v, vio=3.3v, vcore=1.2v, avdd=15.6v, havdd=7.8v, vgh=35v, vgl=-6.0v, hvldo=15.2v, vcom=6.1v, gamma=7.8v, rl=no load) figure 29 . vgh load transient figure 30 . vgh output voltage vs output current figure 31 . vgh ripple voltage -3 -2 -1 0 1 2 3 10 30 50 70 90 110 130 150 output current [ma] output voltage [%] vin=12v avdd=15.6v vgh=35v 5usec/div i out (50ma/div ) i out =50ma vgh (20mv/div ac) v 38.7mv sw (10v/div ) 200usec/div i out (50ma/div ) i out =50ma i out =10ma vgh (200mv/div ac) downloaded from: http:///
19 / 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv typical performance curves (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v, vio=3.3v, vcore=1.2v, avdd=15.6v, havdd=7.8v, vgh=35v, vgl=-6.0v, hvldo=15.2v, vcom=6.1v, gamma=7.8v, rl=no load) figure 32 . vgl load transient figure 33 . vgl output voltage vs output current figure 34 . vgl ripple voltage -3 -2 -1 0 1 2 3 10 30 50 70 90 110 130 150 output current [ma] output voltage [%] vin=12v vgl=-6.0v 5usec/div i out (50ma/div ) i out =50ma v 28.2mv swb1 (10v/div ) 200usec/div i out (50ma/div ) i out =50ma i out =10ma vgl (100mv/div ac) downloaded from: http:///
20 / 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv typical performance curves (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v, vio=3.3v, vcore=1.2v, avdd=15.6v, havdd=7.8v, vgh=35v, vgl=-6.0v, hvldo=15.2v, vcom=6.1v, gamma=7.8v, rl=no load) figure 35 . gpm propagation delay (rise) figure 36 . gpm propagation delay (fal l) figure 37 . gpm clamp voltage (20v clamp) 500usec/div vghm (10v/div ) ctrl (5v/div ) clamp voltage 20v 500nsec/div vghm (5v/div) ctrl (5v/div) delay=255nsec vgh=28v no capacitive load re resister=0 500nsec/div vghm (5v/div) ctrl (5v/div) delay=270nsec vgh=28v no capacitive load re resister=0 downloaded from: http:///
21 / 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv typical performance curves (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v, vio=3.3v, vcore=1.2v, avdd=15.6v, havdd=7.8v, vgh=35v, vgl=-6.0v, hvldo=15.2v, vcom=6.1v, gamma=7.8v, rl=no load) figure 38 . hvldo output voltage vs output current figure 39 . vcom output voltage vs output current figure 40 . gamma output voltage vs output current 500nsec/div vghm (5v/div) ctrl (5v/div) delay=255nsec vgh=28v no capacitive load re resister=0 -3 -2 -1 0 1 2 3 -200 -150 -100 -50 0 50 100 150 200 output current [ma] output voltage [%] vin=12v avdd=15.6v hvldo=15.2v vcom=6.1v -3 -2 -1 0 1 2 3 -20 -15 -10 -5 0 5 10 15 20 output current [ma] output voltage [%] vin=12v avdd=15.6v hvldo=15.2v gamma=7.8v -3 -2 -1 0 1 2 3 0 20 40 60 80 100 output current [ma] output voltage [%] vin=12v avdd=15.6v hvldo=15.2v downloaded from: http:///
22 / 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv typical performance curves (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v, vio=3.3v, vcore=1.2v, avdd=15.6v, havdd=7.8v, vgh=35v, vgl=-6.0v, hvldo=15.2v, vcom=6.1v, gamma=7.8v, rl=no load) figure 41 . vcom slew rate rise figure 42 . vcom slew rate fall figure 43 . vcom dnl vs bit figure 44 . vcom inl vs bit -1 -0.5 0 0.5 1 000h 0ffh bit inl [lsb] -1 -0.5 0 0.5 1 000h 0ffh bit dnl [lsb] 100nsec/div vcom (5v/div ) s/r = 43.3v/us 100nsec/div vcom (5v/div ) s/r = 43.6v/us downloaded from: http:///
23 / 49 tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.co.jp tsz22111 ? 15 ? 001 bm81004muv typical performance curves (unless otherwise specified, ta=25 , avin,vinb1,vinb2,vinb3=12v, vio=3.3v, vcore=1.2v, avdd=15.6v, havdd=7.8v, vgh=35v, vgl=-6.0v, hvldo=15.2v, vcom=6.1v, gamma=7.8v, rl=no load) figure 45 . gamma dnl vs bit figure 46 . gamma inl vs bit -2 -1 0 1 2 000h 3ffh bit inl [lsb] -2 -1 0 1 2 000h 3ffh bit dnl [lsb] downloaded from: http:///
24 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 timing chart on and off sequence of this ic are shown below. vin vl vio vgl en avdd havdd vgh ctrl vghm vin_ uvlo eeprom auto read vl_ uvlo vcore vgl delay (internal) vghm = re vghm = vgh tss_vcore / 3.0ms tss_lsw / 10ms tss_avdd tss_vgh / 7ms load swith on t ear tss_vio / 3.3ms tdly_vgl / 2.5ms vin_ uvlo figure 47 . timing chart vl activates with uvlo release of vin. it reads eeprom data by auto read operation after vl finish its activatio n. (t ear =2msec) after auto read completion, vcore activates. the soft start time of vcore is 3ms ec. after vcore soft-start completion, vio activates. the soft start time of vio i s 3.3msec if the setting is 3.3v. after vio soft-start completion, pg becomes high and vgl activates. ( if swb1 is used) the soft start time of vgl depends on output voltage setting, exte rnal capacitor etc. 2.5msec after vio soft-start completion, load sw turns on (10msec) b ecause of en=high and avdd activates. the soft start time of avdd can be changed by register setting. (10ms ec or 20msec) after avdd started, vgh activates. the soft start time of vgh is 7msec if the setting is 35v. after vgh started, ctrl rising or falling will be a trigger to activate gpm ope ration. when vghm voltage at ctrl =l reaches the gpm clamp voltage, vghm outpu t is high impedance. gpm, vgh, avdd, havdd shuts down when en=low. gpm output (vghm) will be the sa me potential with re. all output shuts down when uvlo of vin is detected. vghm will be the sa me potential with vgh. hvldo, havdd and vcom starts up followed by avdd output voltage. amp 1 to 4 startup followed by hvldo output voltage. when en=low, avdd and havdd output become high impedance. hvldo, vcom and amp1 to 4 output shut down followed by avdd till avdd is below a certain level. figure 48 . timing chart 2 avdd en hvldo havdd vcom amp 1-4 downloaded from: http:///
25 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 example application top view vio amp2 bm81004muv amp1 vdd1 pg sda scl a0 avin hvldo hvcc vdd2 vinb2 vinb1 vinb1 n.c. swb1 swb1 ampgnd amp4 amp3 en vdd3 pgnd3 swb3 n.c. vinb3 re vghm vgh drvp swo swi swsw pgnd pgnd vl comp agnd ctrl vcore havdd vin vin vin avdd vgl swb1 avdd sw vgh c8 c15 r15 c19 l19 c22 c25 dfn1 cfn1 rfn1 cfn2 qn rqn rqp qp dfp2 c28 r30 c31 l35 c35 l39 c39 c3 l3 sw dfp1 cfp3 cfp4 cfp1 rfp1 rfp2 cfp2 vcom inn pgnd2 swb2 drvn vgl pgate avdds c16 d45 c52 c51 c54 c53 c9 c11 c10 avdd c41 c40 c39_0 r39_1 r39_2 figure 49 . example application application circuit components list parts name value company parts number parts name value company parts number c3 4x 10 [uf] murata grm21bb31a106ke18 c40 10 [uf] murata grm31cb31e106ka75 c8 1 [uf] murata grm188b31e105ka75 c41 2x 10 [uf] murata grm31cb31e106ka75 c9 10 [uf] murata grm31cb31e106ka75 c51- 54 0.1 [uf] murata grm188b31h104ka92 c10 10 [uf] murata grm31cb31e106ka75 r15 2.7 [k ] rohm mcr03 c11 10 [uf] murata grm31cb31e106ka75 r30 300 [ ] rohm mcr25 c15 6.8 [nf] murata grm188b11e682ka01 r39_1 330 [ ] rohm mcr03 c16 1 [uf] murata grm188cb31e105ka75 r39_2 120 [ ] rohm mcr03 c19 2x 10 [uf] murata grm31cb31e106ka75 rfn1 2.2 [ ] rohm mcr25 c22 4x 10 [uf] murata grm31cb31e106ka75 rfp1-2 2.2 [ ] rohm mcr25 c25 4.7 [uf] murata grm219b31c475ke15 rqn 100 [k ] rohm mcr03 cfn1 0.1 [uf] murata grm188b31h104ka92 rqp 100 [k ] rohm mcr03 cfn2 470 [pf] murata grm188b11h471ka01 l19 6.8 [uh] taiyo yuden ns10165t6r8n cfp1 0.1 [uf] murata grm188b31h104ka92 l3 6.8 [uh] taiyo yuden nrs8040t6r8m cpf2 0.1 [uf] murata grm188b31h104ka92 l35 6.8 [uh] taiyo yuden nrs8040t6r8m cpf3 1 [uf] murata grm21bb31h105ka12 l39 6.8 [uh] taiyo yuden nrs8040t6r8m cfp4 2.2 [nf] murata grm188b11h222ka01 d45 - rohm rsx301l- 30 c28 10 [uf] murata grm31cb31h106ka12 dfn1 - rohm rb558w c31 10 [uf] murata grm31cb31e106ka75 dfp1 - rohm rb558w c35 2x 10 [uf] murata grm31cb31e106ka75 dfp2 - rohm rb558w c39 4x 10 [uf] mu rata grm21bb31a106ke18 qn pnp rohm 2scr513p c39_0 22 [nf] murata grm188b31h104ka92 qp npn rohm 2sar513p downloaded from: http:///
26 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 protection function explanation of each block 1. buck converter block 1 (vio) 1- 1. over voltage protection (ovp) ovp function is incorporated to prevent ic or other components from m alfunctioning due to rising vio voltage. voltage inputted to vdd1 pin is monitored and if vio voltage reaches vio>110% (t yp ), it is considered as unusual condition thus, ovp function is operated. if ovp is detected, switching is stopped until ovp release voltage (100%, t yp) falls to vio voltage. after ovp is released, switching is re-starte d. 1- 2. over current protection (ocp) if excessive load current (swb1 peak current>3.5a, typ) is pre sent, it limits current to flow to built C in power mos by controlling switching. 1- 3. under voltage protection (uvp) timer-latch type output uvp function is built-in. when unusual condition (vio<80%) is detected, swb1 frequency is d ivided into 1/4 and uvp timer starts. if the unusual condition continues up to 10ms ec (typ), all output will be latched in shutdown state. power reset is needed to remove the latch state and to re -start. 2. buck converter block 2 (vcore) 2-1. over voltage protection (ovp) ovp function is incorporated to prevent ic or other components from ma lfunctioning due to rising vcore voltage. voltage inputted to vdd2 pin is monitored and if vcore volta ge reaches vcore>110% (t yp ), it is considered as unusual condition thus, ovp function is operated. if ovp is detected, switching is stopped until ovp release voltage (100%,typ ) falls to vcore voltage. after ovp is released, switching is re-sta rted. 2- 2. over current protection (ocp) if excessive load current (swb2 peak current>3.0a, typ) is pre sent, it limits current to flow to built C in power mos b y controlling switching. 2- 3. under voltage protection (uvp) timer-latch type output uvp function is built-in. when unusual condition (vcore<80%) is detected, swb2 frequency is divi ded into 1/4 and uvp timer starts. if the unusual condition continues upto 10 ms ec (typ), all output will be latched in shutdown state. power reset is needed to remove the latch state and to re -start. 3. vgl regulator block 3- 1. over current protection (ocp) if excessive load current (i_drvn>5ma, m in) is present, it controls source current (base current of npn tr) of drv n. 3- 2. under voltage protection (uvp) timer-latch type output uvp function is built in. when unusual condition is detected (vgl>80%), uvp time counter get started, and if the unusual condition continues up to 10ms ec (typ), all output is latched in shutdown condition. power reset is n eeded to cancel the latch state and to re-start. downloaded from: http:///
27 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 4. boost converter block (avdd) 4-1. over voltage protection (ovp) ovp function is built in to prevent ic or other components from malfun ctioning due to excessive rise in avdd voltage. the voltage inputted to swo pin is being monitored. if the sw o pin voltage becomes 19.5v (typ), ovp is detected. once ovp is detected, switching is stopped. after avdd voltage falls bel ow ovp detection release voltage 18v (typ), switching is restarted. 4-2. over current protection (ocp) if excessive load current over 5a (typ) of sw peak current is prese nt, ocp limits current to rush to built-in power mos by controlling its output switching. 4-3. under voltage protection (uvp) timer-latch type output uvp function is built in. when an unusual condition is detected (avdd<80%) , uvp timer starts. if the unusual condition continues upto 10 ms ec (typ), all output is latched in shutdown condition . power reset is needed to remove the latch state and to re -start. 4-4. load switch over current protection (lsw_ocp) if excessive load current (7a, typ) is present, it controls curren t of load switch. 5. buck converter block 3 (havdd) 5-1. over voltage protection (ovp) ovp function is incorporated for preventing ic or other components fr om malfunctioning due to rising havdd voltage. voltage inputted to vdd3 pin is being monitored and if havdd voltage reaches havdd>110% (t yp ), it is considered as unusual condition thus, ovp function is operated. if ovp is de tected, switching is stopped until ovp release voltage (100%, typ) falls to havdd voltage. after ovp release, switching is re-start ed. 5- 2. over current protection (ocp) if excessive load current is demanded (swb3 peak current >1.5a, t yp ), it limits current to flow to built C in power mos by controlling switching. 5- 3. under voltage protection (uvp) timer-latch type output uvp function is built-in. when the unusual condition (havdd<80%) is detected, swb3 frequency is divided into 1/4 and uvp timer starts. if the unusual condition continues up to 10ms ec (typ.), all output will be latched with shutdown state. powe r reset is needed to remove the latch state and to re -start. 6. high voltage ldo block 6-1. over current protection (ocp) if excessive load current (i_hvldo>100ma, typ.) is present, it control s source current of hvldo. 6-2. under voltage protection (uvp) timer-latch type output uvp function is built in. when an unusual condition is detected (hvldo<80%) , uvp timer starts. if unusual condition continues up to 10ms ec (typ), all output is latched in shutdown condition. power reset is neede d to remove the latch state and to re -start. 7. vgh regulator block 7-1. over voltage protection (ovp) ovp function is incorporated to prevent ic or other components from ma lfunctioning due to rising vgh voltage. voltage inputted to vgh pin is being monitored and if vg h voltage reaches vgh>38v (t yp ), it is considered as unusual condition so that ovp function is operated. if ovp is detected, l imit drvp curre nt until ovp release voltage (35v, typ) falls to vgh voltage. after ovp release, switching is re-started. 7-2. over current protection (ocp) if excessive load current (i_drvp>5ma, m in) is present, it controls sink current (base current of pnp tr ) of dr vp . 7-3. under voltage protection (uvp) timer-latch type output uvp function is built- in. when an unusual condition is detected (vgh<80%) , uvp timer starts. if the unusual condition continues up to 10 ms ec (typ), all output is latched in shutdown condition. power reset is needed to remove the latch state and to re -start. downloaded from: http:///
28 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 8. general 8- 1. thermal shutdown all outputs will shut down when the ic temperature exceeds 175 (typ). after the temperature falls below 150 (typ), the operation re-starts . 8- 2. vin under voltage lock out vin under voltage lock out prevents the circuit malfunction below the uvlo voltage. if vin voltage is below the uvlo voltage (8.3v / 7.55v), it enters the standby state . downloaded from: http:///
29 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 protection function list block protective function working condition action protective removal buck converter 1 ovp vio>110% stops switching. vio<100% ocp i_swb1>3.5a control switching pulse duty to not over current limit. i_swb1<3.5a uvp vio<80% frequency becomes 1/4 vio>80% ic shutdown if uvp status maintains during 10m sec. ic restart buck converter 2 ovp vcore>110% stops switching. vcore<100% ocp i_swb2>3.0a control switching pulse duty to not over current limit. i_swb2<3.0a uvp vcore<80% frequency becomes 1/4 vcore>80% ic shutdown if uvp status maintains during 10m sec. ic restart vgl regulator ocp i_drvn>5ma limit drvn current. i_drvn<5ma uvp vgl<80% ic shutdown if uvp status maintains during 10msec. ic restart boost converter ovp avdd>19.5v stops switching avdd<18v ocp i_sw>5a control switching pulse duty to not over current limit. i_sw<5a uvp avdd<80% ic shutdown if uvp status maintains during 10msec. ic restart load sw ocp i_swo>7.0a control switching pulse duty to not over current limit. ic restart buck converter 3 ovp havdd>110% stops switching. havdd<100% ocp i_swb3>1.5a control switching pulse duty to not over current limit. i_swb3<1.5a uvp havdd<80% frequency becomes 1/4 havdd>80% ic shutdown if uvp status maintains during 10m sec. ic restart high voltage ldo ocp i_hvldo>100ma limit hvldo current. i_hvldo<100ma uvp hvldo<80% ic shutdown if uvp status maintains during 10msec. ic restart vgh regulator ovp vgh>45v drvp current limit to 0ma vgh<42v ocp i_drvp>5 ma limit drvp current. i_drvp<5ma uvp vgh<80% ic shutdown if uvp st atus maintains during 10msec. ic restart general tsd tj>175 ic shutdown tj<150 uvlo vin<7.55v ic shutdown vin>8.3v downloaded from: http:///
30 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 serial transmission use i 2 c bus control for command interface with host. writing or reading by specifying 1 byte register address besides slav e address. i 2 c bus slave mode format is shown below. start : start condition slave address : send 7 bit data in all with bit of read mode (h) or write mode (l). (msb first) a0 are selectable (1/0) with the slave address select pin. a ck : acknowledge sending or receiving data includes acknowledge bit per byte. if the data is sent and received properly, l is sent and received. if h is sent and received, it means there is no acknowledge. register address : use 1 byte select address. data : data byte. sending and receiving data (msb first) stop : stop condition for writing mode from i2c bus to register, there are single mode and multi -mode. on single mode, write data to one designated register. on multi-mode, as a start address register specified in the se cond byte, writing data can be performed continuously, by entering multiple data. single mode or multi-mode setting can be configured by havi ng or not having stop bit . single mode timing chart s c l s d a _ i n d e v i c e _ o u t s t a r t s l a v e a d d r e s s w r i t e a c k n r e s i s t e r a d d r e s s a c k n a 6 a 5 a 4 a 3 a 2 a 1 a 0 r / w a c k n r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 a c k n d a t a a c k n a c k n s t o p a 6 a 5 a 4 a 3 a 2 a 1 a 0 r / w a c k n r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 a c k n d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k n d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a c k n multi-mode timing chart r/w a a a 0 1 0 0 0 0 a0 0 0 0 0 r/w a a a 0 1 0 0 0 0 a0 1 0 0 0 select register address (8bit) register address data register address data select register address (8bit) stop stop 8bit data 8bit data write operation read operation start start slave address slave address a 5 scl s da _ in de v ice _ o ut s tart s lave ad d re s s w rite a ckn r esi s ter ad d re s s ( ex . 01 h ) a ckn a 6 a 4 a 3 a 2 a 1 a 0 r / w a ckn r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 a ckn d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a ckn d ata ( to r esi s ter 01 h ) a ckn d ata ( to r esi s ter 02 h ) a ckn a 6 a 5 a 4 a 3 a 2 a 1 a 0 r / w a ckn r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 a ckn d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a ckn ? ? ? ? ? ? ? ? ? d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a ckn d a c ( 3 ) m s b yte . d 15 - d 10 have no me anin g a ckn d a c ( 3 ) ls b yte . a ckn d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a ckn s to p ? ? ? ? ? ? ? ? ? d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a ckn d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a ckn d ata ( to r esi s ter 06 h ) d ata ( to r esi s ter 05 h ) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a ckn d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a ckn downloaded from: http:///
31 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 i2ctiming diagram figure 50 . i2c timing diagram ? timing standard values parameter symbol norma lmode fast mode unit min typ max min typ max scl frequency scl - - 100 - - 400 khz scl high time thigh 4.0 - - 0.6 - - us scl low time tlow 4.7 - - 1.2 - - us rise time tr - - 1.0 - - 0.3 us fall time tf - - 0.3 - - 0.3 us start condition hold time thd sta 4.0 - - 0.6 - - us start condition setup time tsu sta 4.7 - - 0.6 - - us sda hold time thd dat 200 - - 100 - - ns sda setup time tsu dat 200 - - 100 - - ns acknowledge delay time tpd - - 0.9 - - 0.9 us acknowledge hold time tdh - 0.1 - - 0.1 - us stop condition setup time tsu sto 4.7 - - 0.6 - - us bus release time tbuf 4.7 - - 1.2 - - us noise spike width tl - 0.1 - - 0 .1 - us tbuf thd : sta tsu ; dat tr tlow thigh thd ; dat tdh tpd tf scl sda ( in ) sda ( out ) tsu ; sta thd ; sta tl tsu ; sto scl sda s p s start bit p stop bit 70 % 30 % 70 % 70 % 30 % 70 % 30 % 70 % 30 % downloaded from: http:///
32 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 command interface eeprom transmission format for data sent and received is shown belo w. i2c write format it can enter further register from 3 byte by entering data continuou sly. data after 0dh is invalid. inputted data reflect to the register at the ack output timing. i2c read format 1. read data from dac register eeprom write format eeprom (dac register) transmission format for write is shown below. eeprom write format r/w a a a 0 1 0 0 0 0 a0 0 0 1 1 1 1 1 1 1 1 0 1 x x x x x x x 0 start slave address register address data stop d 6 to d0 : don t care automatic eeprom read function at start- up upon bm81110m uw start-up, a reset signal is generated and each register is init ialized . after vl activation is finish ed , data which is stored in the eeprom is copied to the regis ters . the automatic eeprom read function at start-up is further explained b y the flow chart below. vl active eeprom read transfer data register start operation figure 51 . automatic eeprom read function at start- up r/w a a a 0 1 0 0 0 0 a0 0 0 0 0 data stop 00h to 0ch n-bytes data start slave address register address r/w a a 0 1 0 0 0 0 a0 0 0 0 r/w a a 0 1 0 0 0 0 a0 1 0 0 data stop 00h to 0ch n-bytes data start slave address register address repeated start slave address downloaded from: http:///
33 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 content of eeprom setting register address bits function default(*1) resolution 00h 6 channel disable register 00h - 01h 6 avdd output voltage setting[5:0] 15.6v [27h] 0.1v [11.7v to 18.0v] 02h 3 avdd ocp offset setting[2:0] 1.6a [04h] 0.4a [0a to 2.8a] 03h 1 avdd soft start time setting[0] 10msec [00h] 10msec [10msec or 20msec] 04h 4 vio output voltage setting[3:0] 3.3v [0bh] 0.1v [2.2v to 3.7v] 05h 6 havdd output voltage setting[5:0] 7.8v [1eh] 0.1v [4.8v to 11.1 v] 06h 5 vgh output voltage setting[4:0] 35v [14h] 0.5v [25v to 40.5 v] 07h 2 gpm clamp voltage setting[1:0] 20v [01h] 5v [15v to 30 v] 08h 5 vgl output voltage setting[4:0] -6.0v [0ah] 0.2v [-10.2v to -4.0v] 09h 6 hvldo output voltage setting[5:0] 15.2v [23h] 0.1v [11.7v to 18.0v] 0ah 8 vcom output voltage setting[7:0] 6.103v[c5h] hvldox0.18/256 [hvldox0.36 to hvldox0.54] 0bh[7:6], 0ch 10 amp1 output voltage setting[9:0] 7.808v[1f2h] hvldo/1024[0v to hvldo] 0bh[5:4], 0dh 10 amp2 output voltage setting[9:0] 7.808v[1f2h] hvldo/1024[0v to hvldo] 0bh[3:2], 0eh 10 amp3 output voltage setting[9:0] 7.808v[1f2h] hvldo/1024[0v to hvldo] 0bh[1:0], 0fh 10 amp4 output voltage setting[9:0] 7.808v[1f2h] hvldo/1024[0v to hvldo] ffh 8 control register[7:0] *1 factory value. *2 value of default voltage setting. the soft start time of each ou tput changes depending on a setting voltage . channel disable register register address = 00h [7] [6] [5] [4] [3] [2] [1] [0] - - vcore havdd vgh vgl gpm av dd_ext 0 enable 1 disable avdd_ext 1 avdd external mode control register register address data [bin] function ffh 1xxx_xxxx write to eeprom from dac register data. x dont care bit register map resister address d7 d6 d5 d4 d3 d2 d1 d0 default 0 0h D D vcore havdd vgh vgl gpm avdd_ext 00h 01 h D D avdd[5:0] 27h 0 2h D D D D D avdd ocp offset[2:0] 04h 0 3h D D D D D D D avdd ss 00h 0 4h D D D D vio [3:0] 0bh 0 5h D D havdd [5:0] 1eh 0 6h D D D vgh [4:0] 14h 0 7h D D D D D D gpm clamp [1:0] 01h 08h D D D vgl [4:0] 0ah 0 9h D D hvldo[5:0] 23h 0ah vcom [7:0] c5h 0 bh amp1[9:8] amp2[9:8] amp3[9:8] amp4[9:8] 55h 0 ch amp1[7:0] f2h 0 dh amp2[7:0] f2h 0 eh amp3[7:0] f2h 0fh amp4[7:0] f2h ffh control register D downloaded from: http:///
34 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 command table 1 01 02 03 04 05 06 07 08 09 [5:0] [2:0] [0] [3:0] [5:0] [4:0] [1:0] [4:0] [5:0] data (hex) avdd [v] avdd ocp offset [a] avdd soft start [msec] vio [v] havdd [v] vgh [v] gpm clamp [v] vgl [v] hvldo [v] 00 11.7 0.0 10 2.2 4.8 25.0 15 -4.0 11.7 01 11.8 0.4 20 2.3 4.9 25.5 20 -4.2 11.8 02 11.9 0.8 2.4 5.0 26.0 25 -4.4 11.9 03 12.0 1.2 2.5 5.1 26.5 30 -4.6 12.0 04 12.1 1.6 2.6 5.2 27.0 -4.8 12.1 05 12.2 2.0 2.7 5.3 27.5 -5.0 12.2 06 12.3 2.4 2.8 5.4 28.0 -5.2 12.3 07 12.4 2.8 2.9 5.5 28.5 -5.4 12.4 08 12.5 3.0 5.6 29.0 -5.6 12.5 09 12.6 3.1 5.7 29.5 -5.8 12.6 0a 12.7 3.2 5.8 30.0 -6.0 12.7 0b 12.8 3.3 5.9 30.5 -6.2 12.8 0c 12.9 3.4 6.0 31.0 -6.4 12.9 0d 13.0 3.5 6.1 31.5 -6.6 13.0 0e 13.1 3.6 6.2 32.0 -6.8 13.1 0f 13.2 3.7 6.3 32.5 -7.0 13.2 10 13.3 6.4 33.0 -7.2 13.3 11 13.4 6.5 33.5 -7.4 13.4 12 13.5 6.6 34.0 -7.6 13.5 13 13.6 6.7 34.5 -7.8 13.6 14 13.7 6.8 35.0 -8.0 13.7 15 13.8 6.9 35.5 -8.2 13.8 16 13.9 7.0 36.0 -8.4 13.9 17 14.0 7.1 36.5 -8.6 14.0 18 14.1 7.2 37.0 -8.8 14.1 19 14.2 7.3 37.5 -9.0 14.2 1a 14.3 7.4 38.0 -9.2 14.3 1b 14.4 7.5 38.5 -9.4 14.4 1c 14.5 7.6 39.0 -9.6 14.5 1d 14.6 7.7 39.5 -9.8 14.6 1e 14.7 7.8 40.0 -10.0 14.7 1f 14.8 7.9 40.5 -10.2 14.8 20 14.9 8.0 14.9 21 15.0 8.1 15.0 22 15.1 8.2 15.1 23 15.2 8.3 15.2 24 15.3 8.4 15.3 25 15.4 8.5 15.4 26 15.5 8.6 15.5 27 15.6 8.7 15.6 28 15.7 8.8 15.7 29 15.8 8.9 15.8 2a 15.9 9.0 15.9 2b 16.0 9.1 16.0 2c 16.1 9.2 16.1 2d 16.2 9.3 16.2 2e 16.3 9.4 16.3 2f 16.4 9.5 16.4 30 16.5 9.6 16.5 31 16.6 9.7 16.6 32 16.7 9.8 16.7 33 16.8 9.9 16.8 34 16.9 10.0 16.9 35 17.0 10.1 17.0 36 17.1 10.2 17.1 37 17.2 10.3 17.2 38 17.3 10.4 17.3 39 17.4 10.5 17.4 3a 17.5 10.6 17.5 3b 17.6 10.7 17.6 3c 17.7 10.8 17.7 3d 17.8 10.9 17.8 3e 17.9 11.0 17.9 3f 18.0 11.1 18.0 : default value register address downloaded from: http:///
35 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 command table 2 register address 0a 0b[7:6], 0c 0b[5:4], 0d 0b[3:2], 0e 0b[1:0], 0f [7:0] [9:0] [9:0] [9:0] [9:0] data (hex) vcom [v] data (hex) amp1 [v] amp2 [v] amp3 [v] amp4 [v] 00 hvldox0.18x(3 - 0/256) 000 hvldox(1 - 0/1024) hvldox(1 - 0/1024) hvldox(1 - 0/1024) hvldox(1 - 0/1024) 01 hvldox0.18x(3 - 1/256) 001 hvldox(1 - 1/1024) hvldox(1 - 1/1024) hvldox(1 - 1/1024) hvldox(1 - 1/1024) 02 hvldox0.18x(3 - 2/256) 002 hvldox(1 - 2/1024) hvldox(1 - 2/1024) hvldox(1 - 2/1024) hvldox(1 - 2/1024) fd hvldox0.18x(3 - 253/256) 3fd hvldox(1 - 1021/1024) hvldox(1 - 1021/1024) hvldox(1 - 1021/1024) hvldox(1 - 1021/1024 ) fe hvldox0.18x(3 - 254/256) 3fe hvldox(1 - 1022/1024) hvldox(1 - 1022/1024) hvldox(1 - 1022/1024) hvldox(1 - 1022/1024 ) ff hvldox0.18x(3 - 255/256) 3ff hvldox(1 - 1023/1024) hvldox(1 - 1023/1024) hvldox(1 - 1023/1024) hvldox(1 - 1023/1024 ) register address ? in case of hvldo=15.2[v] register address 0a 0b[7:6], 0c 0b[5:4], 0d 0b[3:2], 0e 0b[1:0], 0f [7:0] [9:0] [9:0] [9:0] [9:0] data (hex) vcom [v] data (hex) amp1 [v] amp2 [v] amp3 [v] amp4 [v] 00 8.208 000 15.200 15.200 15.200 15.200 01 8.197 001 15.185 15.185 15.185 15.185 02 8.187 002 15.170 15.170 15.170 15.170 c5 6.103 1f2 7.808 7.808 7.808 7.808 fd 5.504 3fd 0.045 0.045 0.045 0.045 fe 5.493 3fe 0.030 0.030 0.030 0.030 ff 5.483 3ff 0.015 0.015 0.015 0.015 step 0.011 step 0.015 0.015 0.015 0.015 register address downloaded from: http:///
36 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 selecting application components 1. buck converter 1-1. selecting the output lc constant figure 52 . inductor current waveform (buck converter). the output inductance (l) is decided by the rated c urrent (i lr ) and maximum input current (i omax ) of the inductance. adjust so that i omax + i l / 2 does not exceed the rated current value. i l can be obtained by the following equation. i l = 1 l (vin - vo ) vo vin 1 f [a] where f is the switching frequency set with sufficient margin because the inductance v alue may have a dispersion of 30%. if the coil current exceeds the rated current (i lr ), the ic may be damaged. 1-2. selecting the input/output capacitor the output capacitor (c o ) smoothens the ripple voltage at the output. selec t a capacitor that will regulate the output ripple voltage within the specifications. output ripple voltage can be obtained by the follow ing equation. vpp = i l r esr i l 2 co vo vin 1 f however, since the aforementioned conditions are based on a lo t of factors, verify the results using the actual product. since the peak current flows between the input and output at the dc/dc c onverter, a capacitor is required to install at the input side. for the reason, the low esr capacitor is recommended as an input capacitor which has the value more than 10f and less than 100m esr. if an out of range capacitor is s elected, the excessive ripple voltage is superimposed o n the input voltage, thus, it may cause the malfunction of the ic. however these conditions may vary according to the load c urrent, input voltage, output voltage, inductance and swi tching frequency. be sure to perform margin check using the actual product. il t ilr i omax mean current i omax + should not exceed the rated value level. S il 2 downloaded from: http:///
37 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 1-3. selecting the output rectifier diode a schottky barrier is recommended as rectifier diode to be u sed at the output stage of the dc/dc converter. select carefully in consideration of the maximum inductor current, maximum output voltage and power supply voltage. maximum inductor current i omax i l 2 diode maximum absolute current maximum inp ut voltage v in diode maximum absolute voltage provide sufficient design margins for a tolerance of 30% to 40 fo r each parameter. 2. boost converter 2-1. selecting the output lc constant figure 53 . inductor current waveform (boost converter). the output inductance (l) is decided by the rated c urrent (i lr ) and maximum input current (i inmax ) of the inductance. adjust so that i in max + i l / 2 does not exceed the rated current value. i l can be obtained by the following equation. f vo vin vo vin l i l 1 1 ? ? ? ? [a] where f is the switching frequency set with sufficient margin because the inductance v alue may have a dispersion of 30%. if the coil current exceeds the rated current (i lr ), the ic may be damaged. 2-2. selecting the output capacitor the output capacitor (c o ) smoothens the ripple voltage at the output. selec t a capacitor that will regulate the output ripple voltage within the specifications. output ripple voltage can be obtained by the follow ing equation. v pp = lmax r esr 1 f co vin vo ? ? ? ? i lmax i l 2 however, since the aforementioned conditions are based on a lo t of factors, verify the results using the actual product. since the peak current flows between the input and output at the dc/dc c onverter, a capacitor is required to install at the input side. for the reason, the low esr capacitor is recommended as an input capacitor which has the value more than 10f and less than 100m esr. if an out of range capacitor is selected, the excessive ripple voltage is superimpose d on the input voltage, thus, it may cause the malfunction of the ic. however these conditions may vary according to the load c urrent, input voltage, output voltage, inductance and swi tching frequency. be sure to perform the margin check using the actual produ ct. il t ilr i omax mean current i omax + should not exceed the rated value level. S il 2 downloaded from: http:///
38 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 2-3. setting phase compensation phase setting procedure. stable negative feedback co ndition is achieved as follows: ? when the gain is set to 1 (0 db), phase delay should not b e more than 150 .consequently, phase margin should not be less than 30 . also, since dc/dc converter applications are sampled according to t he switching frequency, the whole system gbw should be set to not more than 1/10 of the switching frequency. the t arget characteristics of the applications can be summarized as follows: ? when the gain is set to 1 (0 db), the phase delay should not be mo re than 150 . and phase margin should not be less than 30 . ? the frequency when the gain is set to 0 db should not be more th an 1/10 of the switching frequency. the responsiveness is determined by the gbw limitation. consequently, to increase the circuit response, higher switchi ng frequencies are required. avdd is in current mode control. the current mode control is a two-pole sin gle-zero system. the poles are formed by the error amplifier and load while added zero is for phase compen sation. by placing poles appropriately, the circuit can maintain go od stability and transient load respons e. bode plot diagram of general dc/dc converter is described below . at point (a) , gain starts falling via the output impedance of the error amplifier and forms a pole by capacitor c cp . when point (b ) is reached, a zero is formed by resistor r pc and capacitor c cp to cancel the pole by loading and balance variation of gain a nd phase. the gbw (i.e., frequency when the gain is 0 db) is determin ed by phase compensation capacit or connected to the error amplifier. if gbw is to be reduced, increase the capacitance of the capacitor. a f phase margin 0 -90 -180 0 -20db/decade f -90 -180 phase [deg] gain [db] (a) gbw(b) -+ a r3 c1 r1 r2 comp rcp ccp vo figure 54 . setting phase compensation. formed zero (fz1) by r cp resistor and c cp capacitor are shown by using the following equation. and also, feed-forward capacitor c1 and r1 resistor both create form ed zero (fz2) and it is used as boosting phase margin in the limited frequency area. phase lead fz1 = 1 2 ccprcp [hz] phase lead fz2 = 1 2 c1r1 [hz] the formed zero fz2 phase compensation is built into the ic. downloaded from: http:///
39 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 3. positive charge pump : vgh 3-1. selecting the output rectifier diode select carefully in consideration of the maximum load current, maximum output voltage and power supply voltage. maximum output current i omax diode maximum absolute current maximum output voltage avdd diode maximum absolute voltage provide sufficient design margins for a tolerance of 30%~40 for e ach parameter. 3-2. selecting the output pnp transistor select carefully in consideration of the maximum load current, maximum output voltage and power supply voltage. boost converter duty d = avdd vin avdd maximum output current i omax d transistor maximum absolute current power supply voltage avdd x 2 transistor maximum absolute voltage dc gain iomax / ibase transistor hfe power dissipation (doubler mode) ( 2 x avdd C vgh C 2 x vf ) x iout transistor power dissipation power dissipation (tripler mode) ( 3 x avdd C vgh C 4 x vf ) x iout transistor power dissipation maximum drvp current ibase 5 ma provide sufficient design margins for a tolerance of 30%~40 for e ach parameter. 3-3. selecting the base emitter resistor 100k base-emitter resistor used to ensure proper operation. 3-4. selecting the flying capacitor and the switch node resistor a 0.1uf to 0.47uf flying capacitor and 1 to 20 resistor are appropriate for most applications. 3-5. selecting the output capacitor a 10uf ceramic capacitor is appropriate for most application s. more capacitor can be added to improve the load transi ent response. downloaded from: http:///
40 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 4. negative charge pump : vgl 4-1. selecting the output rectifier diode select carefully in consideration of the maximum load current, maximum output voltage and power supply voltage. maximum output current i omax diode maximum absolute current maximum switching voltage vin diode maximum absolute voltage provide sufficient design margins for a tolerance of 30%~40 for e ach parameter. 4-2. selecting the output npn transistor select carefully in consideration of the maximum load current, maximum output voltage and power supply voltage. converter duty d = vin vio vin maximum output current i omax d transistor maximum absolute current power supply voltage vin transistor maximum absolute voltage dc gain iomax / ibase transistor hfe power dissipation (doubler mode) (vin - O vgl O C 2 x vf ) x iout transistor power dissipation maximum drvn current ibase 5 ma pr ovide sufficient design margins for a tolerance of 30%~40 for e ach parameter. 4-3. selecting the base emitter resistor 100k base-emitter resistor used to ensure proper operation. 4-4. selecting the flying capacitor and the switch node resistor a 0.1uf to 0.47uf flying capacitor and 1 to 20 resistor are appropriate for most applications. 4-5. selecting the output capacitor a 10uf ceramic capacitor is appropriate for most application s. more capacitor can be added to improve the load transi ent response. 5. high voltage ldo : hvldo 5-1. selecting the output capacitor a 4.7uf to10uf ceramic capacitor is appropriate for most applicati ons. downloaded from: http:///
41 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 layout guideline dc/dc converter switching line must be as short and thick as possible to reduce line impedance . if the wiring is long, ringing caused by switching would increase and this ma y exceed the absolute maximum voltage ratings . if the parts are located far apart, consider inserting a snubber circuit. the thermal pad on the back side of ic has the great therm al conduction to the chip. so using the gnd plain as br oad and wide as possible can help thermal dissipation. and a lot of thermal via for helping the spread of heat to the di fferent layer is also effective. when there is unused area on pcb, please a rrange the copper foil plain of dc nodes, such as gnd, vin and vout for helping heat dissipation of ic or circumference parts. power dissipation vqfn48v707 0a package on 4-layer 114.3mm 74.2mm 1.6mm glass epoxy pcb (1) 2-layer board (backside copper foil area 74.2 mm 74.2 mm) (2 ) 4-layer board (the 2nd, 3rd layers and backside copper foil area 74.2 mm 74.2 mm) 0 1 2 3 4 5 6 0 25 50 75 100 125 150 ambient temperature : ta [ ] power dissipation : pd [w] (1) 4.01w (2) 5.08w downloaded from: http:///
42 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 i/o equivalence circuit 1, 2, 47, 48. amp1~4 3. vdd1 4.pg 5.sda 6.scl 7.a0 8. avin 9.hvldo 10. hvcc 11.vcom 12. inn 13. ctrl vdd1 vinb1 internal reg. sda internal reg. scl internal reg. ctrl internal reg. a0 avin hvcc vcom inn hvcc hvcc ampx hvcc pg hvcc hvldo hvcc avin downloaded from: http:///
43 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 i/o equivalence circuit - continued 15.comp 16.vl 19, 20.sw 21.swi 22.swo 23.avdds 24.pgate 25.vgl 26.drvn 27.drvp 28.vgh 29.vghm drvp vl vl drvn swi pgate swi avdds swo swo swo swi sw swo swi sw swo swi sw internal reg. comp vgl vl internal reg. vgh vgh vgh vgh vghm re avin vl downloaded from: http:///
44 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 i/o equivalence circuit - continued 30.re 31.vinb3 33. swb3 35. vdd3 36. en 38. swb2 39. vdd2 40. vinb2 41, 42.vinb1 44, 45. swb1 D D D D vdd3 vinb3 vinb3 swb3 swb2 vinb1 swb1 vinb2 vdd2 internal reg. vgh vgh vgh vghm re vinb1 vinb2 vinb3 downloaded from: http:///
45 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 operational notes 1. reverse connection of power supply connecting the power supply in reverse polarity can damage the ic. take precautions against reverse polarity when connecting the power supply, such as mounting an extern al diode between the power supply and the ic s power supply pin s. 2. power supply lines design the pcb layout pattern to provide low impedance sup ply lines. separate the ground and supply lines of the digital and analog blocks to prevent noise in the grou nd and supply lines of the digital block from affecting the analog block. furthermore, connect a capacitor to ground at all pow er supply pins . consider the effect of temperature and aging on the capacitance value when using electrolytic capa citors. 3. ground voltage ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition. 4. ground wiring pattern when using both small-signal and large-current ground traces , the two ground traces should be routed separately but connected to a single ground at the reference point of the application board to avoid fluctuations in the small- signal ground caused by large currents. also ensure that the ground traces of external components do not cause variations on the ground voltage. the ground lines must be as short and thick as possible to reduce line impedance. 5. thermal consideration should by any chance the power dissipation rating be exc eeded the rise in temperature of the chip may result in deterioration of the properties of the chip. in case of exceeding thi s absolute maximum rating, increase the board size and copper area to prevent exceeding the pd rating. 6. recommended operating conditions these conditions represent a range within which the expe cted characteristics of the ic can be approximately obtained . the electrical characteristics are guaranteed under the condi tions of each parameter. 7. inrush current when power is first supplied to the ic, it is possible that the internal logic may be unstable and inrush current may flow instantaneously due to the internal powering sequence and de lays, especially if the ic has more than one power supply. therefore, give special consideration to power c oupling capacitance, power wiring, width of ground wiring, and routing of connections. 8. operation under strong electromagnetic field op erating the ic in the presence of a strong electromagnetic field may c ause the ic to malfunction. 9. testing on application boards when testing the ic on an application board, connecting a capacitor directly to a low-impedance output pin may subject the ic t o stress. always discharge capacitors completely after each process or step. the ics power supply should always be turned off completely before connecting or removing it from the test setup during the inspection process. to prevent damage from static discharge, ground the ic during assembly and use similar precautions during transport and storage. 10. inter-pin short and mounting errors ensure that the direction and position are correct when mountin g the ic on the pcb. incorrect mounting may result in damaging the ic. avoid nearby pins being shorted to each other especially to ground, power supply and output pin . inter-pin shorts could be due to many reasons such as me tal particles, water droplets (in very humid environment) and unintentional solder bridge deposited in between pins du ring assembly to name a few. 11. unused input pins input pins of an ic are often connected to the gate of a mos trans istor. the gate has extremely high impedance and extremely low capacitance. if left unconnected, the elec tric field from the outside can easily charge it. the sma ll charge acquired in this way is enough to produce a signi ficant effect on the conduction through the transistor and cause unexpected operation of the ic. so unless otherwise spe cified, unused input pins should be connected to the power supply or ground line. downloaded from: http:///
46 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 operational notes C continued 12. regarding the input pin of the ic this monolithic ic contains p+ isolation and p substrate la yers between adjacent elements in order to keep them isolated. p-n junctions are formed at the intersection of t he p layers with the n layers of other elements, creating a parasitic diode or transistor. for example (refer to figure below): when gnd > pin a and gnd > pin b, the p-n junction operates as a paras itic diode. when gnd > pin b, the p-n junction operates as a parasitic transistor. parasitic diodes inevitably occur in the structure of the ic. the operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physic al damage. therefore , conditions that cause these diodes to operate, such as applying a voltage lower than the gnd vo ltage to an input pin (and thus to the p substrate) should be avoided. figure 55 . example of monolithic ic structure 13. ceramic capacitor when using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with temperature and the decrease in nominal capacitance due to dc bias a nd others. 14. area of safe operation (aso) operate the ic such that the output voltage, output current, and power dissipation are all within the area of safe operation (aso). 15. thermal shutdown circuit(tsd) this ic has a built-in thermal shutdown circuit that prevent s heat damage to the ic. normal operation should always be within the ics p ower dissipation rating. if however the rating is exceeded fo r a continued period, the junction temperature (tj) will rise which will activate the tsd circuit t hat will turn off all output pins. when the tj falls below the tsd threshold, the circuits are automatically restored to normal o peration. note that the tsd circuit operates in a situation that exceeds th e absolute maximum ratings and therefore, under no circumstances, should the tsd circuit be used in a set des ign or for any purpose other than protecting the ic from heat damage. 16. over current protection circuit (ocp) this ic incorporates an integrated overcurrent protection circui t that is activated when the load is shorted. this protection circuit is effective in preventing damage due to sudden and unexpected incidents. however, the ic should not be used in applications characterized by continuous ope ration or transitioning of the protection circuit. n n p + p n n p + p substrate gnd n p + n n p + n p p substrate gnd gnd parasitic elements pin a pin a pin b pin b b c e parasitic elements gnd parasitic elements c be transistor (npn) resistor n region close-by parasitic elements downloaded from: http:///
47 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 ordering information b m 8 1 0 0 4 m u v ze2 part number package muv:vqfn48v7070a packaging and forming specification ze2: embossed tape and reel marking diagram vqfn48v7070a (top view) 8 1 0 0 4 part number marking lot number 1pin mark downloaded from: http:///
48 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 physical dimension tape and reel information package name vqfn48v7070a ze2 downloaded from: http:///
49 / 49 bm81004muv tsz02201-0313aaf00420-1-2 ? 2014 rohm co., ltd. all rights reserved. 4.dec.2014 rev.002 www.rohm.com tsz22111 ? 15 ? 001 revision history date revision contents 2014. 09.16 001 new release 2014.12.04 002 page 8/49 tsd: min, max added page 9/49 vovp_vio, vovp_vcore and vovp_havdd: min, max added downloaded from: http:///
notice- ge rev.003 ? 2013 rohm co., ltd. all rights reserved. notice precaution on using rohm products 1. our products are designed and manufactured for application in ordinary electronic equipments (such as av equipment, oa equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). if you intend to use our products in devices requiring extremely h igh reliability (such as medical equipment (note 1) , transport equipment, traffic equipment, aircraft/spacecraft, nuclear powe r controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or serious damage to property ( specific applications ), please consult with the rohm sales representative in adv ance. unless otherwise agreed in writing by rohm in advance, rohm s hall not be in any way responsible or liable for any damages, expenses or losses incurred by you or third parties arisin g from the use of any rohm s products for specific applications. (note1) medical equipment classification of the specific app lications japan usa eu china class class class b class class | class 2. rohm designs and manufactures its products subject to s trict quality control system. however, semiconductor products can fail or malfunction at a certain rate. please be sure to implement, at your own responsibilities, adeq uate safety measures including but not limited to fail-safe desig n against the physical injury, damage to any property, whic h a failure or malfunction of our products may cause. the followi ng are examples of safety measures: [a] installation of protection circuits or other protective devic es to improve system safety [b] installation of redundant circuits to reduce the impact of single or multiple circuit failure 3. our products are designed and manufactured for use under standard conditions and not under any special or extraordinary environments or conditions, as exemplified be low. accordingly, rohm shall not be in any way responsible or liable for any damages, expenses or losses arisi ng from the use of any rohms products under any special or extraordinary environments or conditions. if you intend to use our products under any special or extraordinary environments or conditions (as exemplified belo w), your independent verification and confirmation of product performance, reliability, etc, prior to use, must be n ecessary: [a] use of our products in any types of liquid, including water, oils, chemicals, and organi c solvents [b] use of our products outdoors or in places where the products are exposed to direct sunlight or dust [c] use of our products in places where the products are e xposed to sea wind or corrosive gases, including cl 2 , h 2 s, nh 3 , so 2 , and no 2 [d] use of our products in places where the products are exposed t o static electricity or electromagnetic waves [e] use of our products in proximity to heat-producing component s, plastic cords, or other flammable items [f] sealing or coating our products with resin or other coating materials [g] use of our products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of flux is recommended); or washing our products by using water or water-soluble cleaning agents for cleaning residue after soldering [h] use of the products in places subject to dew condensation 4. the products are not subject to radiation-proof design. 5. please verify and confirm characteristics of the final or mou nted products in using the products. 6. in particular, if a transient load (a large amount of load a pplied in a short period of time, such as pulse. is applied, confirmation of performance characteristics after on-board mou nting is strongly recommended. avoid applying power exceeding normal rated power; exceeding the power rating u nder steady-state loading condition may negatively affec t product performance and reliability. 7. de -rate power dissipation (pd) depending on ambient temperature (ta). wh en used in sealed area, confirm the actual ambient temperature. 8. confirm that operation temperature is within the specified range described in the product specification. 9. rohm shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in this document. precaution for mounting / circuit board design 1. when a highly active halogenous (chlorine, bromine, e tc.) flux is used, the residue of flux may negatively affect p roduct performance and reliability. 2. in principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method mu st be used on a through hole mount products. i f the flow soldering method is preferred on a surface-mount p roducts , please consult with the rohm representative in advance. for details, please refer to rohm mounting specification downloaded from: http:///
notice- ge rev.003 ? 2013 rohm co., ltd. all rights reserved. precautions regarding application examples and external circuits 1. if change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the characteristics of the products and external components, inc luding transient characteristics, as well as static characteristics. 2. you agree that application notes, reference designs, and associated data and information contained in this docu ment are presented only as guidance for products use. therefore, i n case you use such information, you are solel y responsible for it and you must exercise your own independ ent verification and judgment in the use of such information contained in this document. rohm shall not be in any way respon sible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of such informat ion. precaution for electrostatic this product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. please take pr oper caution in your manufacturing process and storage so t hat voltage exceeding the products maximum rating will not be applied to products. please take special care under dry co ndition (e.g. grounding of human body / equipment / solder iro n, isolation from charged objects, setting of ionizer, friction prevention and temperature / humidity control). precaution for storage / transportation 1. product performance and soldered connections may deteriorate if the products are stored in the places where: [a] the products are exposed to sea winds or corrosive gases, in cluding cl2, h2s, nh3, so2, and no2 [b] the temperature or humidity exceeds those recommended by rohm [c] the products are exposed to direct sunshine or condensation [d] the products are exposed to high electrostatic 2. even under rohm recommended storage condition, solderab ility of products out of recommended storage time period may be degraded. it is strongly recommended to confirm so lderability before using products of which storage time is exceeding the recommended storage time period. 3. store / transport cartons in the correct direction, which is in dicated on a carton with a symbol. otherwise bent leads may occur due to excessive stress applied when dropping of a c arton. 4. use products within the specified time after opening a hum idity barrier bag. baking is required before using products of which storage time is exceeding the recommended storage tim e period. precaution for product label qr code printed on rohm products label is for rohm s internal use only. precaution for disposition when disposing products please dispose them properly usi ng an authorized industry waste company. precaution for foreign exchange and foreign trade act since our products might fall under controlled goods prescr ibed by the applicable foreign exchange and foreign trade act, please consult with rohm representative in case of export. precaution regarding intellectual property rights 1. all information and data including but not limited to ap plication example contained in this document is for referen ce only. rohm does not warrant that foregoing information or da ta will not infringe any intellectual property rights or any other rights of a ny third party regarding such information or data. rohm shall not be in any way responsible or liable for infringement of any intellectual property rights or other d amages arising from use of such information or data.: 2. no license, expressly or implied, is granted hereby under any i ntellectual property rights or other rights of rohm or any third parties with respect to the information contained in this d ocument. other precaution 1. this document may not be reprinted or reproduced, in whole or in part, without prior written consent of rohm. 2. the products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written consent of rohm. 3. in no event shall you use in any way whatsoever the products and the related technical information contained in the products or this document for any military purposes, includi ng but not limited to, the development of mass-destruction weapons. 4. the proper names of companies or products described i n this document are trademarks or registered trademarks of rohm, its affiliated companies or third parties. downloaded from: http:///
datasheet datasheet notice ? we rev.001 ? 201 5 rohm co., ltd. all rights reserved. general precaution 1. before you use our pro ducts, you are requested to care fully read this document and fully understand its contents. rohm shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny rohms products against warning, caution or note contained in this document. 2. all information contained in this docume nt is current as of the issuing date and subj ec t to change without any prior notice. before purchasing or using rohms products, please confirm the la test information with a rohm sale s representative. 3. the information contained in this doc ument is provi ded on an as is basis and rohm does not warrant that all information contained in this document is accurate an d/or error-free. rohm shall not be in an y way responsible or liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or concerning such information. downloaded from: http:///

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